1. Field of the Invention
This invention relates to a solid-state image pickup device and a fabrication method therefor.
2. Description of the Related Art
In a solid-state image pickup device of the CMOS (Complementary Metal Oxide Semiconductor) type which is one of an image sensor, a region into which light should not be admitted, for example, a region of a black level reference pixel section configured to define the block color to be used as a color reference or a peripheral circuit, is normally shielded from light using a metal wiring line or an optical filter. For example, as a light blocking film formed from a metal wiring line, a wiring having a great line width of several tens to 100 μm is disposed on the uppermost layer above the black level reference pixel section so as to implement a light blocking function.
An example of a light blocking film for a black level reference pixel section which is formed at a copper wiring step or an aluminum wiring step for a multilayer wiring line section is described with reference to FIG. 15 which is a schematic sectional view of a CMOS image sensor in related art and FIGS. 16A and 16B which show a perspective view and a sectional view of part of a light blocking film of the CMOS image sensor of FIG. 15.
Referring to FIG. 15 and FIGS. 16A and 16B, the CMOS image sensor in related art shown includes a light receiving pixel section 112 and a black level reference pixel section 113 each formed from a photodiode on a semiconductor substrate 111, and a multilayer wiring line section 114 formed on an upper face of the light receiving pixel section 112 and the black level reference pixel section 113. The CMOS image sensor is disclosed, for example, in Japanese Patent Laid-Open No. 2006-294991.
The multilayer wiring line section 114 includes a plurality of metal wiring lines 130 formed in a piled relationship in the thicknesswise direction of the multilayer wiring line section 114 from the semiconductor substrate 111 side and including, for example, metal wiring lines 131, 132, 133 and 134, and a interlayer insulating film 140 for isolating the metal wiring lines 130 from one another.
A contact plug 151 is formed in the interlayer insulating film 140 (143) between one of the metal wiring lines 130, for example, the metal wiring line 134, and another one of the metal wiring lines 130 in a lower layer of the metal wiring line 134, for example, the metal wiring line 133. The contact plug 151 connects the metal wiring line 134 and the metal wiring line 133 in the lower layer with respect to the metal wiring line 134 through the interlayer insulating film 143.
Further, an interlayer insulating film 145 is formed in such a manner as to cover over an upper face of that one of the metal wiring lines 130 which is positioned in the uppermost layer, that is, the metal wiring line 134. A pad 161 is formed, for example, from aluminum (Al) on an upper face of the interlayer insulating film 145 and used for electric connection to a peripheral circuit (not shown) or the like.
Meanwhile, a contact plug 152 is formed, for example, from aluminum (Al) in the interlayer insulating film 145 between the pad 161 and the metal wiring line 134 (134c) positioned just below the pad 161. The contact plug 152 extends through the interlayer insulating film 145 to connect the pad 161 and the metal wiring line 134c to each other.
Further, the metal wiring line 134 (134a) is formed in an opposing relationship to the photodiode of the black level reference pixel section 113 and serves as a light blocking film for blocking incidence of light to the photodiode region of the black level reference pixel section 113.
The light blocking film in related art is structured such that a wiring line (metal wiring line 134a) of a great width of several tens to 100 μm is positioned only in the uppermost layer of the wiring line layer while a wiring line pattern is not disposed in the other wiring line layers.
Together with refinement of wiring lines by high integration of LSIs, also reduction of the film thickness of wiring lines is advancing, and in a proposal by an ITRS roadmap in 2005, while the wiring line film thickness of an intermediate layer in LSIs in the 90 nm generation is 225 nm, the wiring line film thickness of an intermediate layer in LSIs in the 65 nm generation is 170 nm.
As enhancement of integration of LSIs advances, also reduction in thickness of the light blocking film itself advances. For example, it is known that, while the light blocking film wherein the wiring line film thickness of an intermediate layer in LSIs in the 90 nm generation proposed by the ITRS roadmap in 2005 is 225 nm exhibits a transmittance of approximately −130 dB, the light blocking film wherein the wiring line film thickness of an intermediate layer in LSIs in the 65 nm generation exhibits another transmittance of approximately −90 dB and exhibits a deteriorated light blocking performance.
Further, in order to reduce the wiring line resistance, copper (Cu) wiring lines have been adopted since the 90 nm generation. Copper wiring line working involves a copper wiring line flattening step by chemical-mechanical polishing (CMP). In the CMP, since the film thickness of a large-width copper (Cu) wiring line is reduced by dishing or erosion, if such wiring line is used as a light blocking film, the light blocking performance is deteriorated.